Evolution of the semiconductor manufacturing industry is placing ever greater demands on yield management and, in particular, on metrology and inspection systems. Critical dimensions are shrinking while wafer size is increasing. Economics is driving the industry to decrease the time for achieving high-yield, high-value production. Minimizing the total time from detecting a yield problem to fixing it determines the return-on-investment for a semiconductor manufacturer.
Fabricating semiconductor devices, such as logic and memory devices, typically includes processing a semiconductor wafer using a large number of fabrication processes to form various features and multiple levels of the semiconductor devices. For example, lithography is a semiconductor fabrication process that involves transferring a pattern from a reticle to a photoresist arranged on a semiconductor wafer. Additional examples of semiconductor fabrication processes include, but are not limited to, chemical-mechanical polishing (CMP), etch, deposition, and ion implantation. Multiple semiconductor devices may be fabricated in an arrangement on a single semiconductor wafer and then separated into individual semiconductor devices.
Metrology processes are used at various steps during semiconductor manufacturing to monitor and control the process. Metrology processes are different than inspection processes in that, unlike inspection processes in which defects are detected on wafers, metrology processes are used to measure one or more characteristics of the wafers that cannot be determined using existing inspection tools. Metrology processes can be used to measure one or more characteristics of wafers such that the performance of a process can be determined from the one or more characteristics. For example, metrology processes can measure a dimension (e.g., line width, thickness, etc.) of features formed on the wafers during the process. In addition, if the one or more characteristics of the wafers are unacceptable (e.g., out of a predetermined range for the characteristic(s)), the measurements of the one or more characteristics of the wafers may be used to alter one or more parameters of the process such that additional wafers manufactured by the process have acceptable characteristic(s).
With increasing pattern density and complexity in advanced technology nodes, automated in-line metrology operations that use a scanning electron microscope (SEM) are claiming an increased share in advanced process control. However, images obtained using SEMs are prone to certain non-uniformities across the field of view (FOV). Most of these non-uniformities are tolerable or negligible for a defect review, classification, or similar exercise. However, such non-uniformities within or across the FOV can lead to systematic or random measurement error in a metrology operation.
Some non-uniformities can include SEM beam-induced distortions that result from beam position error, beam spot size error, stigmation error, or other causes. Some layers that are imaged also can exhibit this behavior due to primary beam deflections at the edges of the FOV. Such errors often can induce image distortions within a single FOV or across multiple FOVs at different parts of the wafer.
FIGS. 5-8 are exemplary SEM images demonstrating non-uniformities or process systematics by comparison. FIG. 5 is a clean image with no visible distortions across the FOV. FIG. 6 is a distorted image with distortions across the FOV. In the contact hole array region of FIG. 6, the contacts at the edge of the FOV are distorted due to an uncalibrated beam used for imaging. Diameter measurement of the distorted contact holes will be affected due to the distortion effects.
FIG. 7 is a clean image without process systematics. The average diameter of the contacts in the FOV is similar FIG. 8 is an image with process systematics. The average diameter of the contacts in the FOV is different. The image of FIG. 8 may be labeled as an undistorted clean image in terms of beam distortions.
To add to the complexity of this problem, many SEM images are averaged across multiple frames. These distortions may not have a constant contribution to the individual frames. The SEM image can exhibit charging artefacts or shows untrue representations of the structures that are imaged.
While these distortions may not be critical for review or classification, the performance of metrology operations can be improved by quantifying and correcting for them. Therefore, improved methods and systems for semiconductor wafer metrology are needed.